Thiết kế logic số (VLSI design) - Quy trình thiết kế trên FPGA

Thiết kế logic số (VLSI design)Bộ môn KT Xung, số, VXL06/2010Quy trình thiết kế trên FPGAISE (Intergrated Software Enviroment)Quy trình thiết kế trên FPGADesign and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;Specification (Lab Experiments)VHDL description (Your Source Files)Functional simulationPost-synthesis simulationSynthesisQuy trình thiết kế trên FPGAImplementationConfigurationTiming simulationOn chip testingVHDL and Schematiclibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity compare_module isPort (value : in std_logic_vector (3 downto 0); res : out std_logic);end compare_module;architecture Behavioral of compare_module issignal std : std_logic_vector (4 downto 0);beginval X"1" ) port map ( I0 => SW8_IBUF_31, I1 => SW7_IBUF_29, O => LED8_OBUF_15 );...Synthesis – Technology Schematic Synthesis – RTL Schematic Synthesis – UCF file# IO location definationNET "HIGH_voltage" LOC = P102;NET "LOW_voltage" LOC = P100;NET "voltage[0]" LOC = P160;NET "voltage[1]" LOC = P161;NET "voltage[2]" LOC = P162;NET "voltage[3]" LOC = P163;# Timing constraintINST "LOW_voltage" TNM = "OUT_REG";INST "HIGH_voltage" TNM = "OUT_REG";NET "voltage[0]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING;NET "voltage[1]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING;NET "voltage[2]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING;NET "voltage[3]" OFFSET = IN 2 ns VALID 0.5 ns BEFORE "CLK" TIMEGRP "OUT_REG" RISING;ImplementationImplementationTranslatePost-translate simulation modelMappingPost-map simulation modelPost-map static TimingPlace & RoutePost-place-route static timingPost-place-route simulation modelTranslateTranslationUCFNGDEDIFNCFNative Generic Database fileConstraint EditorUser Constraint FileNative Constraint FileElectronic Design Interchange FormatCircuit netlistTiming ConstraintsSynthesisMappingChương III FPGAPlace & RouteFPGA VerificationVerificationFunctionTimingOn-circut testingGiao thức truyền tin nối tiếpMáy trạng thái khối UARTSơ đồ khối UARTKhối giao tiếp VGATín hiệu quét VGASơ đồ khối VGA